High-density integrated circuits typically need efficient testing that provides for high failure coverage and low testing costs. Several techniques to add circuitry to integrated circuits for supporting such testing are known as design for testability (DFT) techniques. Many of these DFT techniques are based on scan chain concepts. Scan chains contain memory cells that are connected as shift registers when a scan mode is applied. If no scan mode is applied, the memory cells are not connected as shift registers, and instead perform their application function. The shift registers form a chain from an input that is driven by a test controller to an output that may also be read by the test controller. The test controllers may be implemented externally as part of automated test equipment (ATE) or may be integrated in the integrated circuit that is under test.
In a scan test, data is shifted from the input to the memory cells to put them into a state under which the integrated circuit is to be tested. A test stimulus is applied to let the integrated circuit perform a defined operation to verify the functionality of the integrated circuit. The result of this operation is stored as data in the memory scan cells. After this operation, this data is shifted to the output of the integrated circuit to compare it with expected values.
Integrated circuits may have two or more clock domains, each domain containing circuitry and being driven by a different clock. The clocks differ in phases or frequencies. With DFT techniques, faults that result from signals crossing the border of two clock domains are difficult to detect.
U.S. patent application Pub. No. 2003/0084390 discloses a circuit to test integrated circuits with such different clock domains. The integrated circuit contains a phase-locked loop (PLL) that generates a clock with a frequency that differs from the frequency of external clocks. In the application, several of the clock domains are driven by the PLL.
During the scan test, the shifting of the data is performed by a relatively slow clock that is provided by ATE. The testing stimulus is applied within two sequences, a capture sequence and a launch sequence. In the launch sequence, one or more clock pulses are driven to a clock domain to start an event that changes a signal. In the capture sequence, clock pulses are driven to enable the circuits that receive the signal triggered in the launch sequence.
For the capture and launch clocks, fast pulses are provided to apply test conditions that are close to the application conditions. The capture and launch clocks are provided by the on-chip PLL and a Clock Controller. The clock pulses for the different domains can be either of the same frequency or of frequencies that are multiples of each other.
A problem is how to specify and to generate clock pulses for clock domains that run at different application speeds that are not multiples of each other.